Lower Technology - Analog Layout Laboratory


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Lower Technology


 Lower Technology Demand in market 

People's always wanted to work on cutting edge Technology but still most of the top MNC are working on Finfet technology node and also most of the Consumer Electronics & other electronics products are still on Lower technology node, so always there is market Demand on Lower Technology node.

We Provide all kind of Lower Technology node Training .


This Course is mainly focuses on FinFet layout design techniques used in the physical design of standard cells, Memory layout design and full custom digital and analog blocks. Starting with the FinFet layouting of basic MOS transistors to industry standard project execution in FinFet technologies, the course develops to cover the more advanced techniques used in creating area efficient full custom digital & analog layouts.

Course Outline: 
  • fabrication process Finfet Devices, Cross section view
  • Familiarity with the concepts of FinFet Technologies and processes.
  • Area efficient Layout design of digital & analog cells.
  • Silicon area reduction techniques & reliability techniques.
  • Understanding deep submicron issues.
  • Full custom & digital FinFet floor planning methodologies.
  • Critical Industry standard project execution under the guidance of 6+ year’s industry expert.

Available Technology : 

  • TSMC 16nm - Finfet 
  • TSMC 7nm - Finfet 

Available CAD Tools :

  • Cadence Virtuoso ICADV 20.1 - With Calibre 2021 (DRC/LVS)
Final Project: Serdes with 20ghz, PLL with 2.45 Ghz , DC-DC converter, Data Converter , ADC,DAC

Course Fee : contact admin for price details

Our training Video is listed Below

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